Half Adder ○꠹｜Definition｜1st｜20260605184914-00-⌔

Adder (electronics) - Wikipedia#Half_adder

Half adder

The half adder adds two single binary digits $A$ and $B$. It has two outputs, sum ($S$) and carry ($C$). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is $2C+S$. The simplest half-adder design incorporates an XOR gate for $S$ and an AND gate for $C$. The Boolean logic for the sum (in this case $S$) will be $A\oplus B$ whereas for the carry ($C$) will be $A\cdot B$. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.¹

The truth table for the half adder is:

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Various half adder digital logic circuits:

• Half adder in action.

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• Schematic of half adder implemented with one XOR gate and one AND gate.

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• Schematic of half adder implemented with five NAND gates.

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• Schematic symbol for a 1-bit half adder.

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Printed 2026-06-28.

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Footnotes

1. Lancaster, Geoffrey A. (2004). “10. The Software Developer’s View of the Hardware §Half Adders, §Full Adders”. Excel HSC Software Design and Development. Pascal Press. p. 180. ISBN 978-1-74125175-3. ↩