| A | B |
|---|---|
| Version | ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M |
| Encoding | 32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) |
| Extensions | Thumb, Thumb-2, SVE, SVE2, SME, SME2, Neon, Jazelle, AES, SM3, SM4, SHA, CRC32, RNDR, DSP, Saturated, FPv4-SP, FPv5, Helium; obsolete since ARMv8: Thumb and Jazelle |
| Registers | … |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC) |
| Floating-point | Up to 32 × 64-bit registers,1 SIMD/floating-point (optional) |
ARM AArch32 (32-bit)
(echo:: @ ᯤ)
Footnotes
-
“6.1.2.1 VFP register usage conventions”. Procedure Call Standard for the ARM Architecture. Arm Holdings. 6 October 2023. Retrieved 22 August 2024. ↩