| A | B |
|---|---|
| Designer | AIM |
| Bits | 32-bit/64-bit (32 → 64) |
| Introduced | October 1992 |
| Version | 2.021 |
| Design | RISC |
| Type | Load–store |
| Encoding | Fixed/Variable (Book E) |
| Branching | Condition code |
| Endianness | Big/Bi |
| Extensions | AltiVec, PowerPC AS, APU |
| Successor | Power ISA |
| Registers | … |
| General-purpose | 32 |
| Floating-point | 32 |
| Vector | 32 (with AltiVec) |
PowerPC
(echo:: @ ᯤ)
Footnotes
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“PowerPC Architecture Book, Version 2.02”. IBM. November 16, 2005. Archived from the original on November 29, 2020. ↩