| A | B |
|---|---|
| Designer | Intel, AMD |
| Bits | 16-bit, 32-bit and 64-bit |
| Introduced | 1978 (16-bit), 1985 (32-bit), 2003 (64-bit) |
| Design | CISC |
| Type | Register–memory |
| Encoding | Variable (1 to 15 bytes) |
| Branching | Condition code |
| Endianness | Little |
| Page size | 8086–i286: None i386, i486: 4 KB pages P5 Pentium: added 4 MB pages (Legacy PAE: 4 KB→2 MB) x86-64: added 1 GB pages |
| Extensions | x87, IA-32, x86-64, MMX, 3DNow!, SSE, MCA, ACPI, SSE2, NX bit, SMT, SSE3, SSSE3, SSE4.1, SSE4.2, AES-NI, CLMUL, SM3, SM4, RDRAND, SHA, MPX, SME, SGX, XOP, F16C, ADX, BMI, FMA, AVX, AVX2, AVX-VNNI, AVX-IFMA, AVX512, AVX10, AMX, VT-x, VT-d, AMD-V, AMD-Vi, TSX, ASF, TXT, APX |
| Open | Mixed |
| Registers | … |
| General-purpose | • 16-bit: 8 GPRs, including BP and SP • 32-bit: 8 GPRs, including EBP and ESP • 64-bit: 16 GPRs, including RBP and RSP • 32 GPRs, If CPU supports APX |
| Floating-point | • 16-bit: optional separate x87 FPU • 32-bit: optional separate or integrated x87 FPU, integrated SSE units in later processors • 64-bit: integrated x87 and SSE2 units, later implementations extended to AVX2 and AVX512 |
x86
(echo:: @ ᯤ)