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Don’t-care term - Wikipedia

Don’t-care term

In digital logic, a don’t-care term12 (abbreviated DC, historically also known as redundancies,2 irrelevancies,2 optional entries,34 invalid combinations,546 vacuous combinations,74 forbidden combinations,82 unused states or logical remainders9) for a boolean function is an input-sequence (a series of bits) for which the function output does not matter. An input that is known never to occur is a can’t-happen term.10111213 Both these types of conditions are treated the same way in logic design and may be referred to collectively as don’t-care conditions for brevity.14 The designer of a logic circuit to implement the function need not care about such inputs, but can choose the circuit’s output arbitrarily, usually such that the simplest, smallest, fastest or cheapest circuit results (minimization) or the power-consumption is minimized.1516

Don’t-care terms are important to consider in minimizing logic circuit design, including graphical methods like Karnaugh–Veitch maps and algebraic methods such as the Quine–McCluskey algorithm. In 1958, Seymour Ginsburg proved that minimization of states of a finite-state machine with don’t-care conditions does not necessarily yield a minimization of logic elements. Direct minimization of logic elements in such circuits was computationally impractical (for large systems) with the computing power available to Ginsburg in 1958.17

Printed 2026-06-28.

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Footnotes

  1. Karnaugh, Maurice (November 1953) [1953-04-23, 1953-03-17]. “The Map Method for Synthesis of Combinational Logic Circuits” (PDF). Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics. 72 (5): 593–599. doi:10.1109/TCE.1953.6371932. S2CID 51636736. Paper 53-217. Archived from the original (PDF) on 2017-04-16. Retrieved 2017-04-16. (7 pages) ↩

  2. Phister, Jr., Montgomery (April 1959) [December 1958]. Logical design of digital computers. Digital Design and Applications (3rd printing, 1st ed.). New York, USA: John Wiley & Sons Inc. p. 97. ISBN 0-47168805-3. LCCN 58-6082. MR 0093930. ISBN 978-0-47168805-1. p. 97: […] These prohibited combinations will here be called redundancies (they have also been called irrelevancies, “don’t cares,” and forbidden combinations), and they can usually be used to simplify Boolean functions. […] (xvi+408 pages) ↩ ↩2 ↩3 ↩4

  3. Caldwell, Samuel Hawks (1958-12-01) [February 1958]. Written at Watertown, Massachusetts, USA. Switching Circuits and Logical Design. 5th printing September 1963 (1st ed.). New York, USA: John Wiley & Sons Inc. ISBN 0-47112969-0. LCCN 58-7896. (xviii+686 pages) ↩

  4. Moore, Edward Forrest (December 1958). “Samuel H. Caldwell. Switching circuits and logical design. John Wiley & Sons, Inc., New York 1958, and Chapman & Hall Limited, London 1958, xvii + 686 pp”. The Journal of Symbolic Logic (Review). 23 (4): 433–434. doi:10.2307/2964020. JSTOR 2964020. S2CID 57495605. p. 433: […] what Caldwell calls “optional entries” […] other authors have called “invalid combinations”, “don’t cares”, “vacuous combinations” […] (2 pages) ↩ ↩2 ↩3

  5. Keister, William; Ritchie, Alistair E.; Washburn, Seth H. (1951). The Design Of Switching Circuits. The Bell Telephone Laboratories Series (1 ed.). D. Van Nostrand Company, Inc. p. 147. Archived from the original on 2020-05-09. Retrieved 2020-05-09. [1] (2+xx+556+2 pages) ↩

  6. Marcus, Mitchell Paul [at Wikidata] (c. 1970). “Chapter 6. Tabular method of simplification: Optional combinations”. Written at IBM, Endicott/Binghampton, New York, USA. Switching circuits for engineers. Habana, Cuba: Edicion Revolucionaria, Instituto del Libro. pp. 70–72 [71]. 19 No. 1002. (xiv+2+296+2 pages) ↩

  7. Aiken, Howard H.; Blaauw, Gerrit; Burkhart, William; Burns, Robert J.; Cali, Lloyd; Canepa, Michele; Ciampa, Carmela M.; Coolidge, Jr., Charles A.; Fucarile, Joseph R.; Gadd, Jr., J. Orten; Gucker, Frank F.; Harr, John A.; Hawkins, Robert L.; Hayes, Miles V.; Hofheimer, Richard; Hulme, William F.; Jennings, Betty L.; Johnson, Stanley A.; Kalin, Theodore; Kincaid, Marshall; Lucchini, E. Edward; Minty, William; Moore, Benjamin L.; Remmes, Joseph; Rinn, Robert J.; Roche, John W.; Sanbord, Jacquelin; Semon, Warren L.; Singer, Theodore; Smith, Dexter; Smith, Leonard; Strong, Peter F.; Thomas, Helene V.; Wang, An; Whitehouse, Martha L.; Wilkins, Holly B.; Wilkins, Robert E.; Woo, Way Dong; Little, Elbert P.; McDowell, M. Scudder (1952) [January 1951]. Synthesis of electronic computing and control circuits. The Annals of the Computation Laboratory of Harvard University. Vol. XXVII (second printing, revised ed.). Write-Patterson Air Force Base: Harvard University Press (Cambridge, Massachusetts, USA)/Geoffrey Cumberlege Oxford University Press (London). ark:/13960/t4zh1t09d. Retrieved 2017-04-16. (2+x+278+2 pages) (NB. Work commenced in April 1948.) ↩

  8. Kautz, William H. (June 1954). “Optimized Data Encoding for Digital Computers”. Convention Record of the I.R.E., 1954 National Convention, Part 4 - Electronic Computers and Information Theory. Session 19: Information Theory III - Speed and Computation. Stanford Research Institute, Stanford, California, USA: I.R.E.: 47–57. Archived from the original on 2020-07-03. Retrieved 2020-07-03. [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] (11 pages) ↩

  9. Rushdi, Ali Muhammad Ali; Badawi, Raid Mohammad Salih (January 2017). “Karnaugh-Map Utilization in Boolean Analysis: The Case of War Termination”. Journal of Engineering and Computer Sciences. Qualitative Comparative Analysis. 10 (1). Department of Electrical and Computer Engineering, King Abdulaziz University, Jeddah, Saudi Arabi/Qassim University: 53–88 [54–55, 57, 61–63]. Rabi’II 1438H. Archived from the original on 2021-02-16. Retrieved 2021-02-17. [13] ↩

  10. Morris, Noel Malcolm (January 1969) [1968-12-16]. “Code and Code Converters - Part 2: Mapping techniques and code converters” (PDF). Wireless World. 75 (1399). Iliffe Technical Publications Ltd.: 34–37. Archived (PDF) from the original on 2021-03-09. Retrieved 2020-05-09. [14] ↩

  11. Morris, Noel Malcolm (1969). Logic Circuits. European electrical and electronic engineering series (1 ed.). London, UK: McGraw-Hill. pp. 31, 96, 114. ISBN 0-07094106-8. LCCN 72458600. ISBN 978-0-07094106-9. NCID BA12104142. Retrieved 2021-03-28. p. 31: […] sometimes known as a can’t happen condition […] (x+189 pages) ↩

  12. Association Internationale pour le Calcul Analogique (AICA), ed. (1970) [1969-09-15]. “Systèmes logiques: Conception et applications. Colloque international. Bruxelles, 15-20 septembre 1969. Actes. Design and applications of logical systems. International Symposium. (Brussels, September 15-20 1969). Proceedings, Part 2”. Presses académiques européennes (in English and French). Part 2. Bruxelles, Belgium: Presses Académiques Européennes: 1253. Retrieved 2021-03-28. (xxxiii+650+676 pages) ↩

  13. Holdsworth, Brian; Woods, Clive (2002). Digital Logic Design (4 ed.). Newnes Books/Elsevier Science. pp. 55–56, 251. ISBN 0-7506-4588-2. ISBN 978-0-08047730-5. Retrieved 2020-04-19. (519 pages) [15] ↩

  14. Strong, John A., ed. (2013-03-12) [1991]. “Chapter 2.11 Hazards and Glitches”. Basic Digital Electronics. Physics and Its Applications. Vol. 2 (reprint of 1st ed.). Chapman & Hall/Springer Science & Business Media, B.V. pp. 28–29. ISBN 978-9-40113118-6. LCCN 90-2689. Retrieved 2020-03-30. (220 pages) ↩

  15. Iman, Sasan; Pedram, Massoud (1998) [1997-11-30]. “Chapter 6. Logic Minimization for Low Power”. Written at University of Southern California, California, USA. Logic Synthesis for Low Power VLSI Designs (1 ed.). Boston, Massachusetts, USA/New York, USA: Kluwer Academic Publishers/Springer Science+Business Media, LLC. pp. 109–148 [110]. doi:10.1007/978-1-4615-5453-0_6. ISBN 978-0-7923-8076-4. LCCN 97-042097. Archived from the original on 2024-07-26. Retrieved 2024-07-26. (xv+236 pages) [16] ↩

  16. Maiti, Tapas Kr.; Chattopadhyay, Santanu (2008-05-18). Don’t care filling for power minimization in VLSI circuit testing. 2008 IEEE International Symposium on Circuits and Systems (ISCAS) (1 ed.). Seattle, Washington, USA: Institute of Electrical and Electronics Engineers. pp. 2637–2640. doi:10.1109/ISCAS.2008.4541998. eISSN 2158-1525. ISBN 978-1-4244-1683-7. ISSN 0271-4302. ↩

  17. Ginsburg, Seymour (1959-04-01). “On the Reduction of Superfluous States in a Sequential Machine”. Journal of the ACM. 6 (2): 259–282. doi:10.1145/320964.320983. S2CID 10118067. ↩

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