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Status Register ○꠹｜Definition｜1st｜20251119205401-00-⌔
Status register
In central processing units, a status register, flag register, or condition code register (CCR) is a register that contains a collection of status flag bits. Examples of such registers include the FLAGS register in the x86 architecture, the program status word (PSW) register in the IBM System/360 architecture through z/Architecture, and the application program status register (APSR) in the (32-bit) ARM architecture1 and the NCSV system register in the 64-bit ARM AArch64 architecture.2
The status register contains information about the state of the processor. Individual bits are implicitly or explicitly read or written by the machine code instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction.
Typically, some of the flags in a status register are modified as a result of arithmetic and bit manipulation operations performed by the arithmetic logic unit (ALU). For example, a Z status bit may be set if the result of an operation is zero or cleared if it is nonzero. A string instruction may modify a status flag to indicate whether it terminated due to finding a match or reaching the end of the string. Some flags are used later by conditional instructions to control program execution.
Some CPU architectures, such as the MIPS and Alpha, do not use a dedicated flag register. Others do not implicitly set or read flags. Such machines either do not pass implicit status information between instructions or pass it in a general purpose register.
A status register may have additional fields such as privilege flags, interrupt enable bits, and other types of information. During an interrupt, the status of the currently executing thread can be preserved by storing the current value of the status register (along with the program counter and other active registers) to the machine stack or other memory.
Printed 2026-06-28.
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