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D Flip-Flop ○꠹｜Definition｜1st｜20260604232103-00-⌔
Flip-flop (electronics) - Wikipedia#D_flip-flop
D flip-flop
The D flip-flop is widely used, and known as a data flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change.12 The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.3
Truth table:
(X denotes a don’t care condition, meaning the signal is irrelevant)
Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. Setting S = R = 0 makes the flip-flop behave as described above. Here is the truth table for the other possible S and R configurations:
These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. The advantage of the D flip-flop over the D-type transparent latch is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. An exception is that some flip-flops have a reset signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock.
The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X is shifted into the leftmost bit position.
Printed 2026-06-28.
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Link to original Footnotes
“The D Flip-Flop”. Archived from the original on 2014-02-23. Retrieved 2016-06-05. ↩
“Edge-Triggered Flip-flops”. Archived from the original on 2013-09-08. Retrieved 2011-12-15. ↩
Eckert, J. (1953). “A Survey of Digital Computer Memory Systems”. Proceedings of the IRE. 41 (10): 1393–1406. doi:10.1109/JRPROC.1953.274316. ↩
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