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Full Adder ○꠹｜Definition｜1st｜20260605184914-00-⌔

Adder (electronics) - Wikipedia#Full_adder

Full adder

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as $A$, $B$, and $C_{in}$; $A$ and $B$ are the operands, and $C_{in}$ is a bit carried in from the previous less-significant stage.¹ The circuit produces a two-bit output. Output carry and sum are typically represented by the signals $C_{out}$ and $S$, where the sum equals $2C_{out}+S$. The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers.

A full adder can be implemented in many different ways such as with a custom transistor -level circuit or composed of other gates. The most common implementation is with:

• ✤ $S=A\oplus B\oplus C_{in}$
• ✤ $C_{out}=(A\cdot B)+(C_{in}\cdot (A\oplus B))$

The above expressions for $S$ and $C_{out}$ can be derived from using a Karnaugh map to simplify the truth table.

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. This is because when A and B are both 1, the term $(A\oplus B)$ is always 0, and hence $(C_{in}\cdot (A\oplus B))$ can only be 0. Thus, the inputs to the final OR gate can never be both 1 (this is the only combination for which the OR and XOR outputs differ).

Due to the functional completeness property of the NAND and NOR gates, a full adder can also be implemented using nine NAND gates,² or nine NOR gates.

Using only two types of gates is convenient if the circuit is being implemented using simple integrated circuit chips which contain only one gate type per chip.

A full adder can also be constructed from two half adders by connecting $A$ and $B$ to the input of one half adder, then taking its sum-output $S$ as one of the inputs to the second half adder and $C_{in}$ as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate. The sum-output from the second half adder is the final sum output ($S$) of the full adder and the output from the OR gate is the final carry output ($C_{out}$). The critical path of a full adder runs through both XOR gates and ends at the sum bit $S$. Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to:

• ✤ $T_{\text{FA}}=2\cdot T_{\text{XOR}}=2D$

The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of:

• ✤ $T_{\text{c}}=T_{\text{XOR}}+T_{\text{AND}}+T_{\text{OR}}=D+D+D=3D$

The truth table for the full adder is:

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Inverting all inputs of a full adder also inverts all of its outputs, which can be used in the design of fast ripple-carry adders, because there is no need to invert the carry.³

Various full adder digital logic circuits:

• Full adder in action.

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• Schematic of full adder implemented with two XOR gates, two AND gates, one OR gate.

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• Schematic of full adder implemented with nine NAND gates.

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• Schematic of full adder implemented with nine NOR gates.

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• Full adder with inverted outputs with single-transistor carry propagation delay in CMOS³

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• Schematic symbol for a 1-bit full adder with C${}_{in}$ and C${}_{out}$ drawn on sides of block to emphasize their use in a multi-bit adder

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Printed 2026-06-28.

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Footnotes

1. Mano, M. Morris (1979). Digital Logic and Computer Design. Prentice-Hall. pp. 119–123. ISBN 978-0-13-214510-7. OCLC 1413827071. ↩

2. Teja, Ravi (2021-04-15), Half Adder and Full Adder Circuits, retrieved 2021-07-27 ↩

3. Fischer, P. “Einfache Schaltungsblöcke” (PDF). Universität Heidelberg. Archived from the original (PDF) on 2021-09-05. Retrieved 2021-09-05. ↩ ↩²

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